The recent miniaturization of DRAM (Dynamic Random Access Memory) cells has been accompanied by the necessity of shortening the gate length of access transistors (hereinafter referred to as cell transistors) in cell arrays. However, short channel effects in a transistor become more severe as the gate length is shortened, and drawbacks occur whereby the threshold voltage (Vt) of the transistor is reduced by increased sub-threshold current. When the impurity concentration in the substrate is increased in order to minimize the decrease in Vt, deterioration of the refresh characteristics in the DRAM becomes a severe drawback because of increased junction leakage.
A so-called trench-gate-type transistor (also referred to as a recess channel transistor) in which a gate electrode is embedded in a groove formed on a silicon substrate has been emphasized as a means of overcoming these drawbacks (see Japanese Laid-open Patent Application Nos. 2005-39270 and 2004-95962). Using a trench-gate-type transistor, the effective channel length (gate length) can be physically and adequately maintained, and it is possible to create precision DRAM having a minimum workable dimension of 90 nm or less.
FIG. 16 is a schematic cross sectional view showing an example of the structure of the conventional trench-gate-type transistor. In the cell transistor shown in FIG. 16, a groove (gate trench) 203 is formed in a silicon substrate 201 having an STI (Shallow Trench Isolation) or other element separation region 202, a gate oxide film 204 is formed on the inner wall of this gate trench 203, and a gate electrode 205 is also formed inside the gate trench 203. The gate electrode 205 is composed of a polysilicon film 205a and a silicide layer (or metal film) 205b formed on the polysilicon film 205a, and a high impurity concentration N-type diffusion layer (source/drain region) 206 is formed on both sides of the gate electrode 205 via the gate oxide film 204.
FIG. 17 is a schematic cross sectional view showing another example of the structure of the conventional trench-gate-type transistor. The cell transistor shown in FIG. 17 has an LDD (Lightly Dosed Drain) structure. Specifically, a side wall insulating film 207 is formed on the side surface of the portion of the gate electrode 205 that protrudes from the surface of the silicon substrate 201, wherein the gate electrode is composed of the polysilicon film 205a and the silicide layer (or metal film) 205b formed thereon; a low impurity concentration N-type diffusion layer (LDD region) 208 is formed in the region adjacent to the gate oxide film 204 under the side wall insulating film 207; and a high impurity concentration N-type diffusion layer (source/drain region) 206 is formed in a position that is separated from the gate oxide film 204 by a distance commensurate with the thickness of the side wall insulating film 207.
In the conventional cell transistor structure shown in FIG. 16, the insulation between the gate electrode 205 of the cell transistor and the high impurity concentration N-type diffusion layer (source/drain region) 206 is provided only by the gate insulating film 204. This structure therefore has drawbacks in that defects in electric breakdown resistance can easily occur in the portion P1 in which the aforementioned components are in proximity with each other. In contrast, in the cell transistor structure shown in FIG. 17, not only the gate insulating film 204 but also the low impurity concentration N-type diffusion layer 208 are interposed between the gate electrode 205 and the source/drain region 206. The electric field between the aforementioned components is therefore weakened, and the drawback of inadequate electric breakdown resistance can be overcome. However, even when an LDD structure is employed, fluctuation in transistor characteristics, such as threshold voltage (Vt) or ON current, increases significantly if the gate trench 203 and the gate electrode 205 are misaligned with respect to each other as shown in FIG. 18. The high impurity concentration N-type diffusion layer 206 and the gate electrode 205 also approach each other on one side P2 of the gate electrode 205, causing the drawback of electric breakdown resistance defects to reappear. Furthermore, since the length of the low impurity concentration N-type diffusion layer 208 directly affects the connecting electric field of the cell node, the presence of a misaligned cell transistor causes drawbacks whereby the connecting electric field intensity increases for a portion of the bits, and the information retaining characteristics (tREF characteristics) of the DRAM are severely compromised.